ASAP 2016

The 27th Annual IEEE International Conference on
Application-specific Systems, Architectures and Processors

Jul 6th-8th 2016, London, England

Photo credit: Victor Ochieng, https://www.flickr.com/photos/kijana/1277942908




Important dates:
Abstract due:4th Mar
Paper due:18th Mar
Author notification:27th Apr
Camera ready:20th May
Author registration:20th May
Early registration:8th Jun
Conference:6th-8th Jul
Wednesday 6th July
08:00 - 08:45Registration and breakfast
08:45 - 09:00Welcome Remarks
09:00 - 10:00Academic Keynote: Prof. Andrew Brown, University of Southampton
10:00 - 10:50Paper Session W1
10:50 - 11:10Coffee Break
11:10 - 12:00Paper Session W2
12:00 - 13:15Lunch
13:15 - 14:30Paper Session W3
14:30 - 15:30Poster Session P1
15:30 - 17:10Paper Session W4
18:30 - 21:00Conference Banquet at Ognisko
  
Thursday 7th July
08:30 - 09:15Registration and breakfast
09:15 - 10:15Industrial Keynote: Dr. Georgi Gaydadjiev, Maxeler Technologies
10:15 - 11:30Paper Session T1
11:30 - 12:00Special Session
12:00 - 13:15Lunch
13:15 - 14:30Paper Session T2
14:30 - 15:30Poster Session P2
15:30 - 17:00Paper Session T3
  
Friday 8th July
09:00 - 09:50Paper Session F1
09:50 - 10:50Poster Session P3
10:50 - 11:40Paper Session F2
11:40 - 12:00Closing Remarks

Technical Programme : Papers

Wednesday 6th July
08:45 - 09:00Welcome Remarks
09:00 - 10:00Academic Keynote:
"Event-driven computing"
Prof. Andrew Brown, University of Southampton
10:00 - 10:50Paper Session W1 - Chair : David Thomas
10:00 - 10:25 Compressed L1 Data Cache and L2 Cache in GPGPUs
Ehsan Atoofian
10:25 - 10:37 Temporal Frequent Value Locality
Lois Orosa and Rodolfo Azevedo
10:38 - 10:50 A MPSoC Cache Design Space Exploration Approach Based on ABC Algorithm to Optimize Energy Consumption and Performance
Marcus Vinicius Santos, Edna Barros and Andre Aziz
10:50 - 11:10Coffee Break
11:10 - 12:00Paper Session W2 - Chair : David Thomas
11:10 - 11:35
Adaptive ILP Control to increase Fault Tolerance for VLIW Processors
Anderson Luiz Sartor, Stephan Wong and Antonio Carlos Schneider Beck
11:35 - 11:47
gemV: A Validated Toolset for the Early Exploration of System Reliability
Karthik Tanikella, Yohan Ko, Reiley Jeyapaul, Kyoungwoo Lee and Aviral Shrivastava
11:48 - 12:00 On-Chip Networks for Mixed-Criticality Systems
Polydoros Petrakis, Mohammed Abuteir, Miltos D. Grammatikakis, Kyprianos Papadimitriou, Roman Obermaisser, Zaher Owda, Antonis Papagrigoriou, Michael Soulie and Marcello Coppola
12:00 - 13:15Lunch
13:15 - 14:30Paper Session W3 - Chair Suhaib Fahmy
13:15 - 13:40 Supervised and Unsupervised Machine Learning for Side-Channel based Trojan Detection
Dirmanto Jap, Wei He and Shivam Bhasin
13:40 - 14:05 A Grain in the Silicon: SCA-Protected AES in Less than 30 Slices
Pascal Sasdrich and Tim Güneysu
14:05 - 14:30 OpenCL-Based Erasure Coding on Heterogeneous Architectures
Guoyang Chen, Huiyang Zhou, Xipeng Shen, Josh Gahm, Narayan Venkat, Skip Booth and John Marshall
14:30 - 15:30Poster Session P1
15:30 - 17:10Paper Session W4 - Chair Joshua Levine
15:30 - 15:55Unleashing the Performance Potential of CPU-GPU Platforms for the 3D Atmospheric Euler Solver
Haohuan Fu, Jingheng Xu, Lin Gan, Chao Yang, Wei Xue, Wenlai Zhao, Xinliang Wang and Guangwen Yang
15:55 - 16:20HW/SW-Database-CoDesign for Compressed Bitmap Index Processing
Sebastian Haas, Tomas Karnagel, Oliver Arnold, Erik Laux, Benjamin Schlegel, Gerhard Fettweis and Wolfgang Lehner
16:20 - 16:32Combining GPU and FPGA Technology for Efficient Exhaustive Interaction Analysis in GWAS
Jan Christian Kässens, Lars Wienbrandt, Jorge González-Domínguez, Bertil Schmidt and Manfred Schimmler
16:33 - 16:45Accelerating K-Means Clustering on a Tightly-Coupled Processor-FPGA Heterogeneous System
Tarek Abdelrahman
16:45 - 16:57Design Space Exploration and Constrained Multiobjective Optimization for Digital Predistortion Systems
Lin Li, Amanullah Ghazi, Jani Boutellier, Lauri Anttila, Mikko Valkama and Shuvra Bhattacharyya
16:58 - 17:10A Hardware Accelerator for the Alignment of Multiple DNA Sequences in Forensic Identification
Antonyus Ferreira, João Silva, Jefferson Anjos, Luiz Figueiroa, Edna Barros, Manoel Lima and Victor Medeiros
18:30 - 21:00Conference Banquet at Ognisko
Thursday 7th July
09:15 - 10:15Industrial Keynote:
"Deploying Dataflow Computing in Finance"
Dr. Georgi Gaydadjiev, Maxeler Technologies
10:15 - 11:30
Paper Session T1 - Chair : Lesley Shannon
10:15 - 10:40Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays
Michael Witterauf, Alexandru Tanase, Frank Hannig and Jürgen Teich
10:40 - 11:05Efficient Pointer Management of Stack Data for Software Managed Multicores
Jian Cai and Aviral Shrivastava
11:05 - 11:30A Unified Software Approach to Specify Pipeline and Spatial Parallelism in FPGA Hardware
Jongsok Choi, Ruolong Lian, Stephen Brown and Jason Anderson
11:30 - 12:00Special Session
12:00 - 13:15Lunch
13:15 - 14:30
Paper Session T2 - Chair : Ken Eguro
13:15 - 13:40A multi-beam Scan Mode SAR suitable for satellite operation
Mohammad Reza Mohammadnia and Lesley Shannon
13:40 - 13:52Real Time All Intra HEVC HD Encoder on FPGA
Sachille Atapattu, Namitha Liyanage, Nisal Menuka, Ishantha Perera and Ajith Pasqual
13:53 - 14:05Parameterized System Level Design : Real-Time X-Ray Image Processing Case Study
Tsvetan Shoshkov, Todor Stefanov and Bart Kienhuis
14:05 - 14:17Pipelined FPGA Implementation of Numerical Integration of the Hodgkin-Huxley Model
Roberto Osorio
14:18 - 14:30FPGA-based Frequency Estimation of a DFB laser using Rb Spectroscopy for Space Missions
Christian Spindeldreier, Thijs Wendrich, Ernst Maria Rasel, Wolfgang Ertmer and Holger Blume
14:30 - 15:30Poster Session P2
15:30 - 17:00Paper Session T3 - Chair : Wayne Luk
15:30 - 15:55Synthesisable Recursion for C++ HLS Tools
David Thomas
15:55 - 16:20A Domain Specific Language for Accelerated Multilevel Monte Carlo Simulations
Ben Lindsey, Wayne Luk and Matthew Leslie
16:20 - 16:45F-CNN: An FPGA-based Framework for Training Convolutional Neural Networks
Wenlai Zhao, Haohuan Fu, Wayne Luk, Teng Yu, Shaojun Wang, Bo Feng, Yuchun Ma and Guangwen Yang
16:45 - 16:57Bridging the FPGA Programmability-Portability Gap via Automatic OpenCL Code Generation and Tuning
Konstantinos Krommydas, Ruchira Sasanka and Wu-Chun Feng
Friday 8th July
09:00 - 09:50Paper Session F1 - Chair : Tobias Becker
09:00 - 09:25Deeply Fused Dot-Product Multiplication Architecture
Shmuel Wimer and Israel Koren
09:25 - 09:50Guarding the Guards: Enhancing LNS Performance for Common Applications
Mark Arnold, Ed Chester and John Cowles
09:50 - 10:50Poster Session P3
10:50 - 11:40Paper Session F2 - Chair : David Thomas
10:50 - 11:15New Non-Uniform Segmentation Technique for Software Function Evaluation
Justine Bonnot, Erwan Nogues and Daniel Menard
11:15 - 11:40Parallel floating-point expansions for extended-precision GPU computations
Sylvain Collange, Mioara Joldes, Jean-Michel Muller and Valentina Popescu
11:40 - 12:00Best Paper Award and Closing Remarks

Technical Programme : Posters

Wednesday 6th July
08:45 - 09:00Welcoming Remarks
09:00 - 10:00Keynote
10:00 - 10:50Paper Session W1
10:50 - 11:10Coffee
11:10 - 12:00Paper Session W2
12:00 - 13:15Lunch
13:15 - 14:30Paper Session W3
14:30 - 15:30Poster Session P1
Tetsuo Miyauchi and Kiyofumi Tanaka
Configuration Technique for Adaptability of Multicore Processors on FPGA
Lin Gan, Haohuan Fu, Jingheng Xu, Yu Song, Hongbo Peng and Guangwen Yang
Evaluating the POWER8 Architecture Through Optimizing Stencil-Based Algorithms
Zhinan Cheng, Xi Li, Jiachen Song, Beilei Sun, Xuehai Zhou and Chao Wang
Display Power Reduction for Mobile Closed-Source Games
Shanlin Xiao, Tsuyoshi Isshiki, Dongju Li, and Hiroaki Kenieda
An Efficient Embedded Processor for Object Detection Using ASIP Methodology
15:30 - 17:10Paper Session W4
18:30 - 21:00Conference Banquet at Ognisko
Thursday 7th July
09:15 - 10:15Keynote
10:15 - 11:30Paper Session T1
11:30 - 12:00Special Session
12:00 - 13:15Lunch
13:15 - 14:30Paper Session T2
14:30 - 15:30Poster Session P2
Hend Affes, Amal Ben Ameur, Michel Auguin, François Verdier, and Calypso Barnes
An ESL framework for low power architecture design space exploration
Jose Raul Garcia Ordaz and Dirk Koch
soft-NEON: A Study on Replacing the NEON Engine of an ARM SoC with a Reconfigurable Fabric
Isabela Rossales and Maximiliam Luppe
Architecture for Fractal Dimension Estimation Based on Minkowski-Bouligand Method Using Integer Distances
Ahmed Eissa, Mahmoud Elmohr, Mostafa Saleh, Khaled Ahmed and Mohammed Farag
SHA-3 Instruction Set Extension for A 32-bit RISC Processor Architecture
Maria Silveira, André Araujo and Edna Barros
Temporized Data Prefetching Algorithm for NoC-based Multiprocessor Systems
15:30 - 17:00Paper Session T3
Friday 8th July
09:00 - 09:50Paper Session F1
09:50 - 10:50Poster Session P3
Amine Ait Si Ali, Abbes Amira, Faycal Bensaali, Mohieddine Benammar and Amine Bermak
HW/SW Co-Design Based Implementation of Gas Discrimination
Manish Kumar Jaiswal and Hayden Kwok-Hay So
Architecture for Quadruple Precision Floating Point Division with Multi-Precision Support
Cecil Accetti and Edna Barros
Oolong - A Baseband processor extension to the RISC-V ISA
Teng Yu, Bo Feng, Mark Stillwell, Jose G F Coutinho, Wenlai Zhao, Shuang Liang, Wayne Luk, Alexander Wolf, and Yuchun Ma
Relation-Oriented Resource Allocation for Multi-Accelerator Systems
10:50 - 11:40Paper Session F2
11:40 - 12:00Best Paper Award and Closing Remarks




Important dates:
Abstract due:4th Mar
Paper due:18th Mar
Author notification:27th Apr
Camera ready:20th May
Author registration:20th May
Early registration:8th Jun
Conference:6th-8th Jul